1. Field of the Invention
The present invention relates generally to semiconductors and more specifically to an improved fabrication process for making semiconductor memory devices.
2. Description of the Related Art
In general, memory devices such as a Flash electrically erasable programmable read only memory (EEPROM) are known. EEPROMs are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling.
Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped deeply diffused region and a more heavily doped, shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a xe2x80x9cstacked gatexe2x80x9d structure or word line. The stacked gate structure typically includes: a thin gate dielectric or tunnel oxide layer formed on the surface of a substrate overlying the channel region; a polysilicon floating gate overlying the tunnel oxide; an interpoly dielectric overlying the floating gate; and a polysilicon control gate overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (disposed on the control gate), a poly cap layer (disposed on the silicide layer), and a silicon oxynitride layer (disposed on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.
The process of forming Flash EEPROM cells is well known and widely practiced throughout the semiconductor industry. After the formation of the memory cells, electrical connections, commonly known as xe2x80x9ccontacts,xe2x80x9d must be made to connect the stack gated structure, the source region, and the drain regions to other parts of the chip. The contact process starts with the formation of sidewall spacers around the stacked gate structures of each memory cell. A liner material, typically of a high temperature oxide (HTO), is then formed over the entire substrate, including the stacked gate structure, using conventional techniques, such as chemical vapor deposition (CVD). A dielectric layer, generally of oxide, is then deposited over the etch stop layer, and a layer of photoresist is placed over the dielectric layer and photolithographically processed to form the pattern of contact openings. An anisotropic etch is then used to etch out portions of the dielectric layer to form gate, source and drain contact openings in the dielectric layer. The contact openings stop at the source and drain in the substrate, and the gate contact openings stop at the silicide layer on the stacked gate structure. The photoresist is then stripped, and a conductive material, such as tungsten, is deposited over the dielectric layer and fills the gate, source and drain contact openings. The substrate is then subjected to a chemical-mechanical polishing (CMP) process which removes the conductive material above the dielectric layer to form the contacts through a conductor CMP process.
For miniaturization, it is desirable to dispose adjacent stacked gate structures as closely together as possible. In the conventional process, the formation of the contact mask does not require the use of an anti-reflective coating (ARC) on the dielectric layer. An ARC is typically formed of a material such as silicon oxynitride or silicon nitride and is used for enhancing the imaging effect in subsequent photolithography processing associated with the formation of a contact mask. When the contact size is less than or equal to 0.35 micron, an ARC must be used to meet the increasingly critical dimension requirements of such devices. Since the ARC is not transparent to ultraviolet light, as required for Flash EEPROMs, it must be completely removed after it has performed its function.
One significant problem with using an ARC on the dielectric layer is that after the formation of conductive contacts, the ARC layer needs to be removed in order for the ultraviolet erase process to work on the Flash memories. The conductor CMP removal of the ARC will also remove portions of the conductive contacts as well as the dielectric layer, producing deep scratches therein. The scratches vary significantly from cell to cell, creating non-uniformity and adversely affecting device performance.
A solution, which would selectively remove the ARC from the surface of a dielectric layer over the surface of a substrate for 0.35 micron or sub xe2x88x920.35 micron devices without scratching the dielectric layer and/or conductive contacts formed therein, has long been sought but has eluded those skilled in the art. As miniaturization continues at a rapid pace in the field of semiconductors, it is becoming more pressing that a solution be found.
The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or conductive contacts formed therein by using an oxidizer containing slurry for chemical-mechanical polishing (CMP) of the conductors and a non-oxidizer containing slurry for CMP of the ARC.
The present invention further provides a method for using non-oxidizer slurry to selectively remove an ARC layer in a CMP buffing process without the scratching and/or degradation of a dielectric layer formed over a substrate and of conductive contacts formed in the dielectric layer.
The present invention provides an improved method for making 0.35 micron or sub xe2x88x920.35 micron semiconductor devices.
The above and additional advantages of the present invention will come apparent to those skilled in the art from a reading of the following tailed description when taken in conjunction with the accompanying drawings.